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NXP Semiconductors /LPC5410x /SYSCON /ADCCLKDIV

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Interpret as ADCCLKDIV

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DIV0RESERVED

Description

ADC clock divider

Fields

DIV

ADC clock divider value. 0: Disable ADC clock. 1: Divide by

  1. to 255: Divide by 255.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data